Solid-state image sensors have found widespread use in camera systems. The solid-state imager sensors in some camera systems are composed of a matrix of photosensitive elements in series with switching and amplifying elements. The photosensitive sensitive elements may be, for example, photoreceptors, photo-diodes, phototransistors, charge-coupled device (CCD) gate, or alike. Each photosensitive element receives an image of a portion of a scene being imaged. A photosensitive element along with its accompanying electronics is called a picture element or pixel. The image obtaining photosensitive elements produce an electrical signal indicative of the light intensity of the image. The electrical signal of a photosensitive element is typically a current, which is proportional to the amount of electromagnetic radiation (light) falling onto that photosensitive element.
Of the image sensors implemented in a complementary metal-oxide-semiconductor (CMOS)- or MOS-technology, image sensors with passive pixels and image sensors with active pixels are distinguished. The difference between these two types of pixel structures is that an active pixel amplifies the charge that is collected on its photosensitive element. A passive pixel does not perform signal amplification and requires a charge sensitive amplifier that is not integrated in the pixel.
FIG. 1A illustrates one embodiment of a conventional pixel structure used within a synchronous shutter image sensor. A synchronous shutter image sensor is used to detect the signal of all the pixels within the array at (approximately) the same time. This is in contrast to an asynchronous shutter image sensor that may be implemented with a 3T (three transistor) or 4T (four transistor) pixel structure that does not include a sample and hold stage. Such an asynchronous shutter image sensor outputs the state of a pixel at the moment of read out. This gives movement artifacts because every pixel in the array is not sensing a scene at the same moment.
The pixel structure of FIG. 1A that is used in a synchronous shutter image sensor includes a light detecting stage and a sample and hold stage. The light detecting stage includes a photodiode, a reset transistor, and a reset buffer (e.g., a unity gain amplifier). The sample and hold stage includes a sample transistor, one or more memory capacitors (represented by the capacitor Cmem in FIG. 1A), a sample buffer and a multiplexer, i.e., switch or row select transistor coupled to a column output of the pixel array.
FIG. 1B illustrates one conventional 6 transistor (6T) pixel circuit configuration of the synchronous pixel of FIG. 1A. The reset transistor of the light detecting stage is used to reset the pixel to a high value, and then the voltage on the gate of the source follower transistor M1 starts dropping due to the photocurrent generated in the photodiode. The source follower transistor M1 operates as a unity gain amplifier to buffer the signal from the photodiode. The sample and hold (S&H) stage of FIG. 1B “sample” loads the voltage signal of source follower transistor M1, through the sample transistor, on the memory capacitor (Cmem). The voltage signal from the source follower transistor M1 will remain on the memory capacitor when the sample transistor is turned off. The memory capacitor should be pre-charged to a starting voltage before sampling occurs. The pre-charge transistor serves to pre-charge the voltage on Cmem to a low voltage level upon application of the pre-charge pulse to the gate of the pre-charge transistor, with the source of the pre-charge transistor being tied to ground (GND).
During the frame overhead time, the signal is sampled on the memory capacitor which can be a POD (poly over diffusion), a poly poly capacitor, a MIM (metal insulator metal) capacitor or a transistor which is properly biased to form a stable capacitor during sampling. Due to the second source follower's (M2) threshold voltage (Vt) loss, it is required to pulse Vmem to increase signal swing due to capacitive coupling. During readout, Vmem is pulsed a Vt higher compared to its value during sampling which brings the total pixel swing to the same range as a 3T pixel. As shown in FIG. 1B, a metal line, separate from the supply line VDD, is used to pulse Vmem. The use of a separate metal line may cause a decrease in the fill factor of the pixel (i.e., the ratio of the light sensitive area of the pixel to its total area). In addition, during manufacturing of pixel arrays, the use of this separate metal line for Vmem may cause shorts between Vmem and the supply line VDD, the select line, reset line, or any other signal in the pixel. In the case of Vmem being shorted with the supply line VDD, Vmem becomes the same voltage as VDD, for example, 2.5 volts, and then Vmem can't be pulled up for the sampling and read out of the pixels. The short between Vmem and the supply line results in inoperable rows/columns, which consequently degrades yield during manufacturing of pixel arrays.
FIG. 2 illustrates a timing diagram of the pixel structure of FIG. 1B. The voltage Vprecharge represents the signal applied to the pre-charge transistor to erase the previous sampled value. The voltage Vprecharge may be applied right before the sampling period, right before and extending through the beginning of the sampling period, or only during the beginning of the sampling period to erase the previous sampled value. The voltage Vsample represents the signal applied to the sample transistor and is high during sampling. The voltage Vreset represents the signal applied to the reset transistor and is high during reset. The voltage Vmem is low during sampling and high during reset operation.